Analog Layout Engineer

About the Role

We are looking for an experienced Analog Layout Engineer with strong hands-on exposure to TSMC advanced technology nodes . The candidate should have a solid understanding of full-chip and block-level layout for high-performance analog / mixed-signal IPs.

Key Responsibilities

Perform layout design for Analog, Mixed-Signal, and Custom circuits such as :

PLL, LDOs, ADC / DAC, Bandgap, Amplifiers, High-Speed IO, SerDes blocks

Execute layout of standard cells and custom leaf cells with best practices.

Work on TSMC lower-node constraints including :

Multi-patterning (DPT)

FinFET layout rules

Density rules

EM / IR considerations

Perform layout verification : DRC, LVS, ERC, Antenna, and Physical Verification closure.

Collaborate closely with circuit designers for floorplanning, routing, matching techniques , and optimization.

Handle post-layout simulation (PEX) and iterate for timing / noise / performance closure.

Ensure high-quality documentation of layout structures and design sign-off.

Required Skills

4+ years of hands-on experience in Analog / Mixed-Signal Layout .

Strong experience with Cadence Virtuoso / Virtuoso XL / ASITIC tools .

Proven expertise in TSMC lower-node process technologies (7nm, 5nm, 12nm, 16nm).

Excellent knowledge of :

Layout matching techniques (common-centroid, inter-digitated patterns, shielding, dummy placement)

Parasitic awareness during routing & placement

Latch-up prevention , guard rings , ESD structures

Good understanding of RC extraction, PEX and debugging issues.

Ability to work independently with minimal guidance.

Education

B.Tech / M.Tech in Electronics, VLSI, ECE , or related field.