Rtl Fpga Engineer With Haps Prototyping

Hi We’re looking for an FPGA engineer who knows HAPS inside out and enjoys owning the full stack of prototyping, debug and flow automation. If you like solving tricky timing issues, bringing up complex interfaces, and shaping high-quality prototypes, this one fits you well.

What you’ll work on

Build and debug FPGA prototypes using Synopsys HAPS, ProtoCompiler and Identify.

Develop and review RTL in Verilog / SystemVerilog with a strong verification mindset.

Drive FPGA implementation tasks including synthesis, floorplanning, SDC constraint creation and timing closure.

Handle board bring-up and debug using JTAG, oscilloscopes, logic analyzers and standard lab equipment.

Bring up interfaces like PCIe, DDR, Ethernet and serial buses such as UART, SPI and I2C.

Automate flows using TCL, Python and Shell scripting.

Work closely with design, verification, and validation teams to deliver stable prototypes.

Document your work clearly and keep stakeholders aligned.

Cheers,

Madhu