Senior Design for Debug DV Engineer

As a Sr. SoC Design Verification Engineer , you will be responsible for Design for Debug (DfD) architecture verification related tasks.

Responsibilities :

• Pre-silicon system verification, which includes SoC, FPGA & Full Chip design verification.
• Create testcase and testbench with UVM methodology.
• Full chip / system functional verification, by defining verification strategies / methodology and test plan to enable effective verification.
• Coordinate / interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan.
• Experience on Emulation will be an add on.

Qualifications :