Principal Logic Design Engineer

Principal Logic Design Engineer Location : Bangalore

We are a US based MNC with Market Cap of 10+Billion USD

With over many of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.

We are a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing

As a PE / SPE Logic Design Engineer, you’ll play a pivotal role in designing and implementing some of the the world’s best products. In this full-time role, you’ll report directly to our Logic Design Manager. Our IDC is dedicated to leverage over decades of high-performance memory expertise to deliver cutting-edge memory interface chipset solutions, enhancing memory bandwidth and capacity for data centers and client applications alike, and your contributions will be instrumental in product development.

We offer a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities :

Understand the spec requirements and convert into a micro architecture specification.

Realize the RTL design using Verilog / System Verilog.

Works with verification teams in defining the test plan and reviews the test coverage.

Does pre implementation design checks like lint, CDC, RDC, constraint validation.

Works with physical design team in defining the design and timing constraints and driving implementation till timing closure.

Interact with cross functional circuit teams for new product development

Participate in Architecture level discussions to define the specifications.

Post silicon validation support in bringing up parts.

Requirements / Qualifications :

Minimum 10 years of solid ASIC logic / Digital design expertise with bachelor’s degree or master’s degree

Strong digital design fundamentals.

Strong hands on expertise in HDLs like Verilog / System Verilog.

Experience with EDA tools for simulation, synthesis, and timing analysis and logic equivalence check.

Knowledge of High speed protocols is plus.

Strong scripting abilities using Perl / Tcl / python is a plus

Strong written and verbal communication skills. Able to break down technical concepts to a larger audience is desired.

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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