Senior Design Verification Engineer

Exciting Opportunities in Taras System and Solutions

Role : Senior Design Verification Engineer

Experience : 5+ Years

Location : Anywhere in India

Notice Period : Immediate to 30 days

Key Responsibilities

Develop reusable, scalable SV / UVM testbenches for IP and subsystem-level verification.

Integrate and configure industry-standard DIMM and DFI VIPs (e.g., Synopsys, Cadence) for protocol compliance and functional coverage.

Write and execute test plans, assertions, and coverage models to ensure design correctness and completeness.

Debug simulation failures using waveform viewers and log analysis tools (e.g., Verdi, SimVision).

Collaborate with RTL, firmware, and architecture teams to define verification scope and resolve issues.

Contribute to regression infrastructure, test automation, and coverage closure.

Document verification strategies, test results, and debug findings.

5+ years of experience in SV / UVM-based design verification.

Strong understanding of digital design fundamentals and verification methodologies.

Hands-on experience with DDR DFI and DIMM interface.

Proficiency in scripting languages (Python, Perl, or Shell) for automation.

Familiarity with version control systems (e.g., Git, Perforce) and regression tools.

Preferred Qualifications

Experience with PHY-level verification and DFI interface protocols.

Deep understanding of DDR PHY initialization sequences and firmware loading.

Experience building standalone PHY testbenches integrating DFI and DIMM VIPs.

Knowledge of YAML-based test planning and dashboard integration.

Interested Candidates share your updated resume to gunashree.k@tarassolutions.com