Senior Physical Design Engineer

Job Role : Physical Design Engineer- Senior / Lead

Location : Bangalore, Hyderabad, Noida and Ahmedabad

Experience Required : 5+

ROLE & RESPONSIBILITIES

• Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis atc in ASIC PNR Flow
• Engineer will be responsible for executing the block level place and route assignments from Netlist through GDS flow
• Should be able to do full chip implementation of complex SoCs (RTL-to-GDSII), but it is not must.
• To close STA timing across all corners and modes for blocks and should be able to generate ECO independently.
• Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing.
• Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
• To ensure successful delivery of his block(s) to customers

ESSENTIAL SKILLS & EXPERIENCE

EDUCATION BACKGROUND

ABOUT eInfochips (An Arrow Company) :

eInfochips, an Arrow company (A $30B, NASDAQ listed (ARW); Ranked #102 on the Fortune List), is a leading global provider of product engineering and semiconductor design services. 25+ years of proven track record, with a team of over 2500+ engineers, the team has been instrumental in developing over 500+ products and 40M deployments in 140 countries. Company’s service offerings include Silicon Engineering, Embedded Engineering, Hardware Engineering & Digital Engineering services. eInfochips services 7 of the top 10 semiconductor companies and is recognized by NASSCOM, Zinnov and Gartner as a leading Semiconductor service provider.