Ip / Soc Verification Engineer

Senior Verification Engineer Email : prabhu.p@acldigital.com

WhatsApp : 8754387484

Location : Bangalore (Hybrid — 2 days / week onsite)

Notice Period : Less than 30 days only

Experience - 5 - 30 Years

JD 1 — Requirement : 1 Requirement

Role : Senior Design Verification Engineer (15+ Years Experience) (Designation Based on the Final Discussion will decide with mutual understanding)

Qualifications :

BE / BTech / MTech in EE / EC / ECE

Required Skills :

15+ years of hands-on Design Verification experience

Strong expertise in verification of various IPs and SoCs

Excellent experience with Verilog

Strong experience in SystemVerilog & UVM methodology

Good understanding of SoC verification , C , and related verification flows

JD 2 — Requirement : 2 Req

Role : Design Verification Engineer (8+ Years Experience)

Qualifications :

BE / BTech / MTech in EE / EC / ECE

Required Skills :

8+ years of Design Verification experience

Strong experience in IP Verification , SystemVerilog , and UVM

Excellent knowledge of DV concepts and fundamentals

Hands-on experience with Verilog

Strong understanding of SoC verification , C , and SV / UVM methodology

JD 3 — Requirement : 4 Req

Role : Design Verification Engineer (5+ Years Experience)

Qualifications :

BE / BTech / MTech in EE / EC / ECE

Required Skills :

5+ years of Design Verification experience

Experience in IP or SoC DV

Strong understanding of DV fundamentals

Hands-on experience with Verilog

Mandatory experience with SystemVerilog & UVM methodology