Senior Staff Design Verification Engineer

Description :

Key Responsibilities :

• Lead SoC and subsystem-level functional verification activities from planning to closure.
• Define verification strategies, methodologies, and environments using SystemVerilog and UVM.
• Develop and maintain scalable, reusable UVM-based testbenches for complex IPs and SoCs.
• Drive verification plans for high-speed interfaces like PCIe, CXL, AMBA (AXI, AHB, APB), and CPU subsystems.
• Define and implement coverage-driven and assertion-based verification methodologies (CDV / ABV).
• Own coverage closure, regression analysis, and final sign-off metrics for quality and completeness.
• Debug complex functional, performance, and timing issues in collaboration with design and validation teams.
• Execute and oversee Gate-Level Simulations (GLS), waveform analysis, and issue triaging.
• Evaluate and adopt emerging verification methodologies and tools to improve efficiency and scalability.
• Contribute to verification automation frameworks, flow enhancements, and continuous improvement initiatives.
• Act as a technical mentor and reviewer for mid-level and junior DV engineers.
• Collaborate with program managers and cross-functional stakeholders to ensure timely project delivery.

Technical Skills & Expertise :

Leadership & Soft Skills :

(ref : hirist.tech)