Analog Engineer- Layout

About the Company

We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision. This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simulation concepts. The engineer will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.

About the Role

We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology.

Responsibilities

• Own end-to-end schematic-to-layout design for high-speed analog and mixed-signal circuits.
• Perform floor planning, bump and pad-ring design, and ESD implementation at the chip level.
• Collaborate with SoC, circuit, and digital design teams for layout integration and signoff.
• Ensure layouts meet all DRC, LVS, ERC, EM / IR and reliability standards.
• Handle layout matching, shielding, and parasitic optimization for high-speed performance.
• Support simulation correlation and assist in debugging layout-related circuit issues.
• Work independently, taking full ownership of assigned IPs and layout deliverables.

Qualifications

Required Skills

Preferred Skills

Pay range and compensation package

Location : Remote / India (must support USA / Canada time zone)

Travel : Willing to travel to the U.S. for project release (as required)

Equal Opportunity Statement

We are committed to diversity and inclusivity.

Skills Required

shielding , Pvs, Cadence Virtuoso