Hi,
We have an opening for FPGA Design engineer role - Bangalore
REQUIRED : EXP : 5 to 12 years
Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog / System Verilog based testbench development
Experience with AMD Vivado & Vitis SDK & VItis AI tools.
Experience with C / C++ in developing Embedded FW & scripting automation using Python
Experience with Petalinux build flow, familiarity with Uboot, linux driver changes and FPGA SoC debugging.
Please share your resume to jayalakshmi.r2@ust.com
Regards,
Jaya
For For Bangalore • Hosur, Tamil Nadu, India