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ASIC SOC RTL Design Lead (Micro-architecture)
ASIC SOC RTL Design Lead (Micro-architecture)Eximietas Design • Bengaluru, Karnataka, India
ASIC SOC RTL Design Lead (Micro-architecture)

ASIC SOC RTL Design Lead (Micro-architecture)

Eximietas Design • Bengaluru, Karnataka, India
30+ days ago
Job description

Hi All,

Greetings' from Eximietas Design....!

We are Hiring ASIC SOC RTL Design Engineer / Leads.

Job Title : ASIC SOC RTL Design Engineer / Leads ..!

Experience : 8+ Years.

Location : Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.

Anyone with a Valid H1B or Already in US.

Job Description :

Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a critical role in defining and implementing the microarchitecture of cutting-edge semiconductor designs. You will work on complex RTL design challenges, collaborate with cross-functional teams, and contribute to the delivery of high-performance, power-efficient, and innovative solutions.

Key Responsibilities :

  • Define and develop microarchitecture specifications for complex SoC designs.
  • Lead RTL design and implementation using Verilog / SystemVerilog, ensuring optimal performance, power, and area (PPA).
  • Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution.
  • Perform design trade-off analysis to meet functional, performance, and power requirements.
  • Develop and implement design methodologies to improve efficiency and quality.
  • Mentor and guide junior engineers, fostering a culture of innovation and excellence.
  • Participate in design reviews, provide technical leadership, and ensure adherence to project timelines.

Qualifications :

  • 8+ years of hands-on experience in RTL design and microarchitecture development.
  • Strong expertise in RTL design using Verilog / SystemVerilog and logic synthesis .
  • Proficiency in microarchitecture design for complex SoCs, including pipelining, caching, and memory subsystems .
  • Experience with low-power design techniques (e.g., clock gating, power gating, multi-Vt optimization).
  • Familiarity with advanced process nodes and their specific challenges (e.g., finFET, multi-patterning).
  • Strong scripting skills in Tcl, Python, or Perl for automation and flow development.
  • Excellent problem-solving skills and attention to detail.
  • Strong communication and leadership skills.
  • What We Offer :

  • Opportunity to work on cutting-edge semiconductor designs and innovative technologies.
  • Collaborative and inclusive work environment.
  • Competitive compensation and benefits package.
  • Professional growth and development opportunities.
  • Interested Engineers please share your updated resume :

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    Soc Rtl Design Lead • Bengaluru, Karnataka, India

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