Senior Verification Engineer
Email : prabhu.p@acldigital.com
WhatsApp : 8754387484
Location : Bangalore (Hybrid โ 2 days / week onsite)
Notice Period : Less than 30 days only
Experience - 5 - 30 Years
๐ JD 1 โ Requirement : 1 Requirement
Role : Senior Design Verification Engineer (15+ Years Experience) (Designation Based on the Final Discussion will decide with mutual understanding)
Qualifications :
- BE / BTech / MTech in EE / EC / ECE
Required Skills :
15+ years of hands-on Design Verification experienceStrong expertise in verification of various IPs and SoCsExcellent experience with VerilogStrong experience in SystemVerilog & UVM methodologyGood understanding of SoC verification , C , and related verification flows๐ JD 2 โ Requirement : 2 Req
Role : Design Verification Engineer (8+ Years Experience)
Qualifications :
BE / BTech / MTech in EE / EC / ECERequired Skills :
8+ years of Design Verification experienceStrong experience in IP Verification , SystemVerilog , and UVMExcellent knowledge of DV concepts and fundamentalsHands-on experience with VerilogStrong understanding of SoC verification , C , and SV / UVM methodology๐ JD 3 โ Requirement : 4 Req
Role : Design Verification Engineer (5+ Years Experience)
Qualifications :
BE / BTech / MTech in EE / EC / ECERequired Skills :
5+ years of Design Verification experienceExperience in IP or SoC DVStrong understanding of DV fundamentalsHands-on experience with VerilogMandatory experience with SystemVerilog & UVM methodology