Senior Principal Design Verification Engineer (PCIe Gen6 / Gen5)

Senior Principal Design Verification Engineer (India) / Principal Design Verification Engineer

Bangalore (Hybrid ) / Hyderabad (Hybrid )

Company Background

We are one among 49 US AI startups that have raised $100M or more in 2024

We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems / software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I / O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics.

Summary

Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers.

We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing.

Roles and Responsibilities

• Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage.
• Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device.
• Define and implement infrastructure for effective HW / SW co-simulation.
• Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements.
• The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms.

Skills / Qualification

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"