Senior Design Verification Engineer (Design For Debug)

Job Description :

As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and / or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.

Responsibility

• Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
• Create testcase and testbench with UVM methodology
• Fullchip / system functional verification, by defining verification strategies / methodology and test plan to enable effective verification
• Coordinate / interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
• Experience on Emulation will be an add on.

Qualifications :

Contact :

Ms. Anna - WhatsApp +84935059669

Email : anh.thivannguyen@ust.com