Responsibilities
- Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY module
- Verifying the IP integration with dedicated simulation environment
- Development and support test cases of different verification environments
- Support worldwide customers on the IP integration
- Get familiar to existing verification process, propose improvements
- Maintain the traceability from the customer specification or the product specification to the architecture and verification results.
- Track and maintain verification productivity metrics
- Reporting periodically on progress and difficulties
Qualifications
Positive and self-driven achiever with :
Can Do" AttitudeBachelor or Master's degree in Electronics Engineering, Computer Science, or related disciplinesStrong analytical and problem-solving skillsExcellent interpersonal skillsOpen for traveling abroadWork in international organization and specially with teams in France, USA, Taiwan and IndiaBecause Rambus operates internationally, very good English is important for the positionYour technical experience :
6+ years experience verification with Verilog, SystemVerilog, FPGA prototyping6+ years experience with complex ASIC / VLSI verification6+ years experience with Avery or UVM. Any 3rd party VIP experience is a plus.6+ years experience in multinational companyExperience with creating documentation, python, shell & etc.About Rambus
Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.