Position Overview :
The High-Density Flash team supplies Non-Volatile Memory (NVM) IP’s to numerous SoC groups within the company.These IP’s include analog macro cells and sophisticated digital controllers. We are seeking a highly skilled and experienced Design Verification Engineer to drive verification of our digital controllers and for test chips using our NVM IP. The ideal candidate will have a strong background in digital verification, digital design, and an understanding of memory and NVM technologies. As a team member, you will help deliver robust integrated NVM designs which meet functional, performance, power, and reliability goals.
Key Responsibilities :
Technical :
- Develop test plans to fully verify IP functionality and features, working with IP digital and analog designers, SoC designers, and the NVM IP test team
- Implement test methodologies including Verilog / System-Verilog testbenches, constrained-random and directed tests, assertion-based checking, coverage metrics and clock domain crossing verification
- Perform RTL and GLS simulation along with debug and metric evaluation.
- Define and review verification methods for efficient use of time and compute resources - Drive innovation allowing for optimal test
- Innovate methods for robust integrated verification of NVM components, including digital controller, analog memory, charge pumps, LDOs, oscillator, and built-in test features
Project Management :
Plan and manage project schedules, deliverables, and milestones for digital verification projects.Ensure verification environment meets technical specifications, project timelines, and quality standards.Identify and mitigate verification risks and gaps, ensuring design and test requirements are fully met.Collaboration and Communication :
Work closely with digital design team to align verification environment with design requirements.Present verification methodology, metrics and reviews to stakeholders and management.Communicate pre-silicon verification methods to post-silicon test team for use on ATE and testbench.Interface with SoC teams to optimize methods used for NVM IP verification.Qualifications : Education :
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.Experience :
5+ years of experience in digital design verification.Experience with NVM is a plus.Technical Skills :
Expertise in methods of digital design verification, including test of state machine, clock domain crossing, data path and control functionalityGood understanding of digital design and modelling (Verilog / VHDL) - Familiarity with analog circuitry (charge pump, LDO, oscillator) is beneficialKnowledge of VLSI memory design and operation - Familiarity with NVM operation, including programming, erasing, and reading is a plusProficient in digital simulation tools (e.g., Cadence Xcelium, Cadence Vmanager) and modelling tools (e.g., Verilog / System Verilog, UVM, SVA)Ability to use programming languages (PERL, TCL, Python) to automate work flowsOther Skills :
Strong analytical and problem-solving skillsExcellent verbal and written communication skillsEffective time management skills that enable on-time project deliveryAbility to work in teams and collaborate effectively with people in different functionsAbility to work effectively in a fast-paced and rapidly changing environmentAbility to take the initiative and drive for resultsDesirable :
Knowledge of digital implementation methods, including logic synthesis, place and route, and static timing analysisExperience in silicon bring-up, debug, and characterization