Design Verification Engineer

Job Title : Design Verification Engineer (DV / SoC / IP)

Experience : 5–15 years

Location : Bangalore

Employment Type : Full-time

About the Role :

We are looking for an experienced Design Verification Engineer to join our ASIC / SoC hardware design team. You will be responsible for developing advanced verification environments, writing test plans, executing simulations, and ensuring that digital designs meet all functional requirements before tape-out. This role requires deep technical expertise, strong debugging skills, and the ability to work closely with cross-functional design teams.

Key Responsibilities :

Develop comprehensive verification plans based on design specifications.

Build and maintain reusable verification environments & testbenches using SystemVerilog / Verilog and UVM methodologies.

Write, debug, and execute test cases, perform simulations, regression testing, corner-case verification, and debug design failures.

Perform functional and code coverage analysis, ensuring coverage goals are met and driving closure.

Collaborate with RTL designers, physical design teams, and other stakeholders to ensure design correctness.

Participate in design / code reviews and provide feedback for improvements.

Mentor and guide junior verification engineers.

Required Qualifications & Skills :

Bachelor’s or Master’s degree in Electrical, Electronics, Computer Engineering, or related field.

5 to 15 years of hands-on experience in IP / SoC / RTL verification.

Strong expertise in SystemVerilog / Verilog, UVM, and modern verification methodologies.

Solid understanding of digital design concepts and RTL development flows.

Strong analytical, debugging, and problem-solving skills with a focus on corner-case scenarios.

Excellent communication skills with the ability to work effectively in cross-functional teams.