Role : Design Verification Engineer(DV)
Domain : VLSI / Semiconductor
Skillset Expectation : Design Verification, Digital Verification, SOC verification, ASIC verification
Mandatory Expectation : UVM and Verilog / VHDL
Experience : 4 to 12 years
Available Work Location : Bangalore, Chennai, Hyderabad, Noida, Kochin only
Design Verification Engineer • Bengaluru, Karnataka, India