Senior Lead

Tessolve – Physical Design Engineer (5+ Years Experience)

Location : Bangalore

Job Type : Full-time

Experience : 5–10 years

Domain : ASIC / SoC Physical Design

Job Summary

We are looking for an experienced Physical Design Engineer with strong expertise in ASIC / SoC implementation flows including floor planning, synthesis, place & route, timing closure, and sign-off. The candidate should have hands-on experience working on advanced technology nodes (7nm / 5nm / 16nm) and delivering high-quality, tapeout-ready designs.

Key Responsibilities

Physical Design Implementation

• Perform RTL-to-GDSII implementation including synthesis, floor planning, placement, CTS, routing, physical verification, and sign-off.
• Develop and optimize block-level and / or top-level floorplans considering area, power, and performance targets.
• Drive clock tree synthesis with skew, insertion delay, and power optimizations.
• Execute place-and-route in Cadence Innovus / Synopsys ICC2 or equivalent tools.

Timing Closure & Power Optimization

Sign-off & Verification

Cross-Functional Collaboration

Required Skills & Experience