Dft Lead Engineer

Large Design Servicess Organization with more than 1000 employees TITLE : DFT Lead Engineer

LOCATION : GREATER BENGALURU AREA

As a DFT Lead, you will be responsible for defining, developing, and executing DFT strategies to ensure high test coverage and reliable silicon performance. You will lead DFT activities throughout the project lifecycle, collaborate with design and verification teams, and mentor junior engineers to deliver high-quality solutions that meet customer requirements.

Key Responsibilities

Define and implement DFT architectures and methodologies for SoC / ASIC designs.

Develop and execute test plans, ATPG patterns, and BIST architectures.

Establish scan, boundary scan (JTAG), MBIST, LBIST, and compression methodologies.

Optimize test coverage and ensure compliance with manufacturing test requirements.

Insert and verify DFT structures using industry-standard EDA tools (Synopsys, Cadence, Mentor, etc.).

Perform ATPG pattern generation, fault simulation, and diagnosis.

Debug DFT-related design issues during simulation and post-silicon validation.

Coordinate with backend and verification teams to ensure DFT integrity and timing closure.

Collaborate closely with RTL design, physical design, and verification teams throughout the development cycle.

Interface with test engineering and foundry teams for bring-up and production testing.

Ensure DFT deliverables meet project milestones and quality targets.

Lead a team of DFT engineers and provide technical guidance, reviews, and best practices.

Conduct knowledge-sharing sessions to upskill team members in emerging DFT technologies.

Support business and client engagements by providing technical expertise during project proposals and reviews.

Required Skills & Technical Expertise

Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan (IEEE 1149.1).

Hands-on experience with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, Tessent, or Modus.

Proficiency in fault coverage analysis, compression techniques, and test optimization.

Familiarity with Verilog / VHDL, scripting languages (TCL, Perl, Python) for automation.

Strong analytical and debugging abilities to resolve complex DFT and test issues.

Ability to analyze design specifications and derive efficient test methodologies.

Excellent communication and client-facing skills. Demonstrated ability to lead and mentor junior engineers.

Collaborative mindset and proven ability to work in cross-functional team environments.

Exposure to consulting or customer engagement projects is a plus.

Qualifications

8- 15 years of hands-on experience in DFT implementation and validation in the semiconductor industry.

Experience with ASIC / SoC design flows and post-silicon test processes preferred.

Prior experience in leading small to medium DFT teams is highly desirable.

Work on cutting-edge semiconductor technologies and global projects.

Uday

muday_bhaskar@yahoo.com

"Mining the Knowledge Community"