Principal RTL Design Engineer

Staff / Principal RTL Design Engineer : -

Bangalore

Founded in 2023,by Industry veterans HQ in California,US

• We are revolutionizing sustainable AI compute through intuitive software with composable silicon
• Job Description

o As a member of Design(RTL) team, you will be responsible for the microarchitecture and design of IPs / Controllers for SoC / SiP designs.

o Perform architectural / design trade-offs for required product features,

performance and system constraints.

o Responsible for defining and documenting design specifications.

o Develop and deliver a fully verified RTL to achieve the design targets and quality

sign-off requirements.

o Design and Implement logic functions that enable efficient test and debug.

o Provide Debug support for design verification and post-silicon activities.

o Minimum 10 + years industry experience with Master’s degree (preferred) or

Bachelors degree in Electrical or Computer Engineering.

o Hand-on experience with micro-architecture and RTL development (System

Verilog) for x86 / ARM CPU Processors or high-speed custom ASICs / Accelerators

with focus on any one : Cache controller, IO interfaces (PCIe, CXL, Ethernet),

UCIe, Memory controllers, Display, Video encoding / transcoding.

o Good understanding of ASIC design flow including RTL design, verification, logic

synthesis and timing analysis and sign-off quality flows.

o Self-starter with strong interpersonal and communication skills .

o Excellent team player.

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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