RTL Design Engineer

Roles and Responsibilities :

Developing high-quality RTL code using Verilog / SystemVerilog for complex digital blocks.

Collaborating across architecture, verification, and physical design teams.

Driving synthesis, CDC, linting, and timing closure activities.

Participating in design reviews and micro-architecture discussions.

Debugging issues in both pre- and post-silicon environments and supporting bring-up.

Optimizing for area, power, and performance.

Experience Required :

Bachelor’s / Master’s in Electronics, Electrical, or Computer Engineering.

4+ years of hands-on RTL design experience in ASIC / FPGA environments.

Strong skills in Verilog / SystemVerilog and digital design fundamentals.

Familiarity with tools like Design Compiler, Spyglass, VCS, etc.

Good grasp of Synthesis, STA, and power-performance trade-offs.

Exposure to AMBA protocols (AXI, AHB, APB) is a plus.

Immediate or short notice joiners preferred.

Job Location : Noida

Experience Required : 4+ Years

Notice Period : Immediate Joiners