Design Verification Engineer - PCIe / NVMe

We’re hiring a Verification Engineer to own PCIe / NVMe verification for next-gen storage products. You’ll build UVM environments, drive protocol validation for PCIe Gen5 / 6 / 7 and NVMe, close coverage, debug complex issues, and ensure production-ready verification quality in collaboration with design and architecture teams.

Job Description :

Seeking an experienced Verification Engineer (8+ years) with hands-on PCIe Gen5 / 6 / 7 and NVMe protocol expertise for Microchip. Develop SystemVerilog / UVM testbenches, execute protocol-level verification with strong focus on compliance, coverage, and random stimulus. Perform functional coverage analysis, constraint-random testing, and debug across design / validation teams. Collaborate to resolve interface / protocol issues and own verification plans, strategies, and documentation for high-speed digital and storage interfaces.

If you want to contribute to industry-leading PCIe / NVMe products and own impactful verification, this role is a strong fit.

Regards,

Karthik Kumar