Analog Mixed-Signal IO Lead

About the Company

We are seeking a highly skilled and motivated IO Design Expert with deep experience in designing GPIOs, specialty analog / digital IOs, and ESD protection circuits across technology platforms ranging from BCD technologies (e.G., 180nm / 130nm / 55nm) to advanced CMOS nodes (e.G., 28nm, 16nm, 12nm, 7nm, 5nm). You will play a critical role in the architecture, schematic design, layout oversight, simulation, verification, and qualification of IO libraries for complex SoCs with stringent reliability and performance requirements.

About the Role

Architect and design a wide range of IO cells :

General Purpose IOs (GPIOs)

High-Speed IOs (LVDS, CML, SSTL, HSTL, etc.)

Power IOs (e.G., VDD, VSS pads)

Analog IOs for sensor interfaces, ADC / DAC connections

ESD protection devices and clamps (CDM, HBM, MM compliance)

High-voltage tolerant IOs (for BCD technologies)

Responsibilities

Collaborate with system architects and package designers to define pad ring structure, signal assignments, and power integrity constraints.

Lead IO library development, including reusable IP blocks across multiple SoCs and technology platforms.

Perform corner simulations (PVT, aging, mismatch) and electrostatic discharge simulations to ensure design robustness.

Validate designs through post-layout verification, LVS / DRC, and EM / IR checks.

Work with layout engineers to guide physical design and ensure DFM compliance.

Interface with foundries for tapeout, IP sign-off, and PDK updates.

Lead silicon characterization, correlation with simulations, and root-cause analysis for silicon issues.

Ensure compliance with automotive (AEC-Q100), industrial, and consumer qualification requirements when applicable.

Required Skills

Deep experience in designing GPIOs, specialty analog / digital IOs, and ESD protection circuits.

Preferred Skills

Experience with BCD technologies and advanced CMOS nodes.