Senior Tech Lead - DV

Job Requirements

Design Verification professional with a proven track record in leading DV projects for complex SoC / ASIC / FPGA designs. This role will be working closely with world class engineering teams to ensure design quality, performance, and verification closure on cutting-edge hardware products.

Key Responsibilities

Lead the DV team in planning, developing, and executing verification strategies for SoC / ASIC designs.

Collaborate with architects, RTL designers, and validation engineers to define verification requirements and methodologies.

Develop and maintain verification environments using UVM / SystemVerilog.

Drive code reviews, functional coverage analysis, and regression tracking to achieve verification sign-off.

Debug complex issues across hardware and simulation environments.

Mentor junior engineers and ensure adherence to industry best practices.

Interface with Meta's internal teams for status reporting, issue tracking, and delivery milestones.

Required Skills & Qualifications

Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.

10+ years of hands-on experience in ASIC / SoC Design Verification.

Strong expertise in SystemVerilog, UVM, and simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).

Solid understanding of digital design, SoC architecture, and verification methodologies.

Experience with constrained random verification, functional coverage, and assertion-based verification.

Proven leadership skills managing DV teams and interacting with global clients.

Strong problem-solving skills, analytical mindset, and attention to detail.

Work Experience

Required Skills & Qualifications :

Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.

10+ years of hands-on experience in ASIC / SoC Design Verification.

Strong expertise in SystemVerilog, UVM, and simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).

Solid understanding of digital design, SoC architecture, and verification methodologies.

Experience with constrained random verification, functional coverage, and assertion-based verification.

Proven leadership skills managing DV teams and interacting with global clients.

Strong problem-solving skills, analytical mindset, and attention to detail.

Skills Required

Uvm, systemverilog