Senior Design Verification Engineer (Europe)

Must-Have :

Strong in

SystemVerilog, UVM , functional coverage & constrained-random verification

• Experience with

Portable Stimulus / Cadence Perspec

• Good understanding of

digital design ,

MCU / SoC architectures

• Hands-on with

simulation & debug tools

• Strong analytical and communication skills

Good to Have :

• Automotive / safety-critical IC background
• Knowledge of

ISO 26262

Python scripting , regression automation, flow optimization