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This position is in HSV (Hardware System Verification) group in the SVG (System Verification Group) of Cadence. The team is working on Protium - FPGA based prototyping platforms.

Team is responsible for developing FPGA IPs for Protium platform, including architecture, design, verification, integration, timing closure, documentation and releasing the IPs to end users.

The Principal Design Engineer is responsible for FPGA IP Design, Verification / Simulation, Timing closure, Validation of IP on the hardware.

Enhancements to current IPs as well as developing new IPs.

Required experience :

• Master degree in Electrical Engineering with 6 + years of experience or bachelor degree with 8+ years
• Experience with FPGA design and verification using Verilog
• Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route
• Experience in debugging FPGAs in the lab using Vivado hardware manager
• Experience using Linux servers, Script development using Shell / Perl / TCL
• Experience using Cadence Simulators Incisive or Xcellium
• Detailed knowledge about one or more industry standard interfaces such as PCI Express, DRAM / DDR4, SRAM, I2C, JTAG, AXI desired.

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