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FPGA
Tejas NetworksBangalore, Gurgaon, Mumbai30+ days ago
Job descriptionGood understanding of FPGA Transceiver architecture is must Good understanding of FPGA Clock-networks and hands-on timing closure exposure is must. Proficiency in high-speed FPGA designs Experience with DDR / PCIe / SPI / XGMII / XFI buses is must4. RTL front end design experience in Verilog and / or VHDL and / or SV is must5. Experience in verification / simulation tools is must Experience in micro-architecture design / development is must Strong Lab-skills and high-speed FPGA debug techniques are preferred Exposure to system-design is preferred Good at understanding different standard documents from IEEE, ITU-T is preferred Strong digital design concepts Knowledge of OTN technology (ITU-T G.709) is highly preferred Hand-on experience with EDA tools on timing closure is preferred Good at Static timing analysis, timing constrains, clock-domain crossing
Requirement : -
Roles and Responsibilities :
- You will be engaged in end-to-end system development involving complex modules - related to carrier-grade optical transmission / Ethernet switch / aggregation / wireless product development.
- You will work very closely with Product-Line Management team, Product Verification team to understand the customer requirement to incorporate innovativeness and value-additions to product development.
- You will refer standards, plan and execute the module level design and verification.
- You will also work closely with HW & SW architects to understand and influence the module level design / architecture and implement the design changes in Verilog or SV.
- You will validate the design and work closely with other teams / members still the product verification cycle.
Skills :
Good to have skills :