Physical Design Engineer - RTL / GDS

Job Description :

We are looking for a skilled Physical Design Engineer to join our team and be responsible for RTL-to-GDSII implementation of high-performance SoCs at advanced technology nodes (e.g., 28nm, 16nm, 7nm, 5nm). You will work closely with RTL designers, DFT engineers, and verification teams.

Key Responsibilities :

• Perform RTL synthesis, floorplanning, power planning, placement, CTS (Clock Tree Synthesis), routing, and signoff (timing, noise, power, DRC / LVS).
• Work on multi-voltage / multi-clock domain designs and apply UPF-based power intent.
• Collaborate with cross-functional teams to handle constraints, timing budgets, and physical verification issues.
• Perform physical verification including DRC, LVS, and ERC.
• Handle static timing analysis (STA) and resolve timing violations.
• Optimize for area, power, and performance while meeting project deadlines.
• Debug and fix tool setup, design rule issues, and signoff criteria.

Skills and Qualifications :

1. Synopsys (ICC2, DC, PrimeTime)

2. Cadence (Innovus, Genus, Tempus)

3. Mentor Graphics (Calibre for DRC / LVS)

Keywords for Naukri / LinkedIn Search :

ref : hirist.tech)