Exp : - 6-10 years experienced in DFx verification .
The job description is good experience in RTL verification and debug, GLS simulations and debug, Verilog coding experience, good understanding on JTAG and verification in Testmode. It's good to have pattern generation and Silicon debug experience. Please let me know if you have suitable profiles.
please share your resume to Jayalakshmi.r2@ust.com
Regards,
Jaya
Dfx Verification • Greater Bengaluru Area, India