Senior Analog Layout Engineers

Key Responsibilities : Include the development and preparation of multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering.

• Working on layout design of owned blocks with Cadence Virtuoso XL.
• Working on block and top-level level layout verification with Calibre.
• Extensive PAD Ring and Top / Chip leve l layout experience
• Working with analog / mixed-signal and digital design teams to ensure proper layout design
• Block level floor planning and layout
• IC top level floor planning and area estimation
• Using recommended layout and verification techniques, tools, and flows to produce optimal designs
• Generate post-layout extraction
• Create layout related documentation and conduct layout reviews
• Interact with packaging team to generate clean bonding diagram that complies with assembly rules

Education & Experience :

Key Qualifications :

Skills Required

Digital Design, Tcl Scripting