Responsibilities :
- Work as part of the Design Enablement team, closely collaborating with SoC cross-functional teams
- Define and develop PDN and PV flows and methodologies for low geometry nodes (3nm, 5nm, 16nm)
- Manage requirements and define tools and flows needed for SoC-level implementation
- Collaborate with EDA vendors to evaluate and benchmark latest PDN & PV tools and methodologies
- Lead deployment and adoption of new tools, flows, and methodologies across the organization
- Act as a change agent in introducing innovative flow improvements and process standardization
Skills Required
Pv, Physical Verification