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(Urgent) RTL FPGA Design Engineer
ACL DigitalHyderabad, Telangana, India16 hours ago
Job description
RTL FPGA Design Engineer
Experience : 2-4 years
Location : Hyderabad
FPGA architecture
Vivado Flow
Scripting and automation
Verilog / VHDL
HW debugging
We are looking for some background of scripting and or conceptual understanding of Power for experienced candidates.
Interested,please share your updated resume to janagaradha.n@acldigital.com
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Rtl Design Engineer • Hyderabad, Telangana, India
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