Senior design verification engineer

This is a full-time role for a Senior Design Verification Engineer for Brainchip’s Hyderabad, India Office. This role is responsible for performing functional verification. Key tasks include debugging, ensuring designs meet customer requirements, documenting verification plans, and collaborating with cross-functional teams to improve the verification process.

Responsibilities

Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.

Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

Come up with test plans, tests and verification infrastructure for complex IPs / sub-systems.

Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.

Perform functional coverage driven verification closure.

Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Qualifications

B. Tech / M. Tech. with 5-10 years of relevant experience.

Experience in verification of complex IPs / units and sub-systems.

Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.

Expertise in Verilog.

Knowledge in System Verilog or similar hardware verification language.

Familiarity with verification methodologies like UVM and exposure to industry standard verification tools for simulation and debug.

Experience with System Verilog Assertion (SVA) a plus.

Experience with Perl, Python or other scripting language is a plus

Experience with Industry Standard protocols like I2 C / SPI / GPIO / AXI / APB / AHB is a plus