Staff, design verification - cpu cluster / soc

We're looking for a passionate and hands-on RISC-V CPU Cluster / So C DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who You Are

• You thrive in building robust verification environments using System Verilog, UVM and C++, and can define and drive verification plans independently.
• You bring a system-level mindset, with experience integrating multiple IPs into clusters or So Cs and verifying their interactions.
• You have a strong grasp of stimulus planning, debug techniques, and coverage closure for verifying complex hardware subsystems like caches, No Cs, and memory hierarchies.
• You’re comfortable working on features that span multiple IPs — such as coherence, security — and ensuring their correct behavior at the cluster or So C level.

What We Need

What You Will Learn