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Opening for Design Verification Lead- Bangalore

Opening for Design Verification Lead- Bangalore

USTBengaluru, Karnataka, India
30+ days ago
Job description

Hi All,

JD for Design Verification Lead : -

  • Good understanding of verification concepts and techniques. Very good knowledge of Verilog / System Verilog and UVM.
  • Experience and knowledge in Verification of IP’s related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols.
  • Verification for complex IP’s and close the Verification to the challenging milestones.
  • Strong knowledge of AXI4 / AXI5 protocol
  • Strong understanding of Coherency rules in ACE and ACE5
  • Experience with architecting BFMs / VIPs
  • Should be able to handle a team of 3-4 engineers
  • IP Verification : VR creation as per the chip requirements and UVM / OVM Test benches creation
  • Support in building verification infrastructure at the chip level as per the requirements
  • Capable of handling multiple areas of IP Verification : RTL, Power Aware and Gate Level Verification

Please do share your resume to jayalakshmi.r2@ust.com

Regards,

Jaya

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Design Verification Lead • Bengaluru, Karnataka, India