Physical Design Lead

Desired Skills and Experience :

• B. Tech. / M. Tech. with 3-10 years of experience in Physical Design
• The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on an SOC design
• Should have handled Netlist to GDS II implementation at Chip / partition level for atleast 2-3 designs
• Hands-on expertise with technology nodes like 28nm, 16nm and below
• Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre
• Excellent understanding of design partitioning & budgeting along with hands-on experience in Chip / partition floor planning, placement optimizations, Clock planning and routing.
• Good understanding of low power implementation techniques and static low power checks
• IO ring design and bump planning is a plus
• Being proficient in TCL, Perl scripting is a plus