Senior Design Verification Lead

Hello VLSI folks!

HCL Engineering - Semiconductor - Hiring Design Verification Engineer (Senior Level - 5 to 20Years years' experience) - Chennai, Bangalore.

Interested aspirants could email your profile to [HIDDEN TEXT] / Call 8050996119.We will discuss in details on the job profile & responsibilities.

Company : HCL Tech

Job Summary :

We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies.

Responsibilities :

• Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification)
• Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals
• Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis
• Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution
• Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team
• Champion best practices for verification code quality and participate in code reviews
• Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies
• Provide technical leadership and contribute to the overall verification roadmap for the team

Qualifications :

Benefits :

Thanks & Regards,

Magenderan.R

Manager - Talent Acquisition

HCLTech - ERS- Bangalore – Semiconductor

Email : [HIDDEN TEXT]

Ph : 8050996119

Skills Required

Verification Tools, Simulators, formal verification, Vhdl, Verilog, Design Verification, Scripting Languages, Uvm