STA Engineer

JD For STA Engineer-5+ years’ experience

• Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs.
• Can work closely with FE team for constraints development and constraints cleanup.
• Work with partitions / block owner to give timing ECO for timing closure.
• Knowledge of advanced timing closure techniques and methodology
• Knowledge of industry standard tools from Synopsys or Cadence.
• Worked on DSM technologies, tsmc 5nm and below experience preferred.
• Minimum 5+ years of relevant experience
• Good scripting and communication skills