Ip verification engineer

Job Title : IP Verification Engineer – UVM verificationExp Level : 4+ yrsLocation : Bangalore / HyderabadJob Description : System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.Basic Job Deliverable : Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / RivieraSV / UVM Functional verificationExpertise in Vivado for simulation debugsQualification : B. E / M. E / M. TechInterested can Share CV to