Should have experience in FPGA based systems / sub-systems.
Should have experience in working with LDRA tool for static and dynamic analysis.
Should have experience in working with Vivado / Vitis / Xilinx tools.
Good experience in WBS, effort estimations and SVN.
Should have managed DO-254 based IV&V activity of complete software lifecycle artefacts.
Should have done B.E / B.Tech from recognized university / College.
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Engineer • India
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