Job Title : SoC GLS Engineer (Gate-Level Simulation) – UVM Expertise Required
Location : Bangalore / Noida
Notice Period : Immediate Joiners Only
Job Description
We are looking for an experienced SoC GLS (Gate-Level Simulation) Engineer with strong hands-on expertise in UVM-based verification . The ideal candidate will have deep understanding of SoC design flows, GLS methodologies, SDF handling, debugging, and sign-off processes. This role requires the ability to work in a fast-paced environment, collaborate with cross-functional teams, and ensure high-quality verification and GLS sign-off.
Key Responsibilities
Perform Gate-Level Simulations (GLS) for complex SoC designs including SDF annotation, debug, and sign-off.
Develop, enhance, and maintain UVM testbenches for GLS environments.
Run GLS regressions, analyze failures, and deliver high-quality debug reports.
Work closely with RTL, STA, PD, and DFT teams to resolve timing, CDC, and initialization issues.
Ensure testbench readiness, coverage closure, and alignment with verification plans.
Support tape-out activities with rigorous GLS checks and validation procedures.
Required Skills & Experience
4 – 15+ years of experience in SoC verification and GLS.
Strong hands-on experience in UVM, SystemVerilog , and functional verification methodologies.
Deep knowledge of GLS flows , simulation debugging, and SDF annotation.
Experience with industry-standard simulators (VCS, NCSim, Xcelium, Questa, etc.).
Good understanding of RTL-to-GDSII flow, STA interactions, and clock / reset architectures.
Ability to work independently and drive GLS sign-off.
Preferred Skills
Experience with low-power verification, UPF, and CDC analysis.
Familiarity with scripting languages (Python / Perl / Shell) for automation.
Exposure to SoC integration and IP-level GLS.
Why Join Us?
Opportunity to work on cutting-edge SoC programs.
High-impact role with major contribution to tape-out.
Collaborative and growth-oriented work culture.
Contact Details
Prabhu P
Phone : 8754387484
Email : prabhu.p@acldigital.com
ACL Digital – Semiconductor Division
Verification Engineer • Bengaluru, Karnataka, India