Design Verification Engineer

Key Responsibilities :

• Develop and maintain SystemVerilog / UVM verification environments for both SoC and IP-level components.
• Design and implement reusable testbench components including drivers, monitors, scoreboards, and sequencers.
• Create and execute functional and scenario-based test cases to validate complex hardware logic and system-level behaviors.
• Develop and maintain functional coverage models to ensure verification completeness and drive coverage closure.
• Write and integrate SystemVerilog Assertions (SVA) for both dynamic simulation and formal verification.
• Perform detailed failure analysis and debugging at both IP and SoC levels using industry-standard tools such as Synopsys Verdi and Cadence SimVision.
• Work closely with RTL designers and architects to understand design intent, identify corner cases, and provide continuous feedback throughout the development cycle.
• Collaborate with cross-functional teams to validate complex features, performance metrics, and ensure protocol compliance across Skills and Experience :
• 4 to 10 years of hands-on experience in ASIC / FPGA / SoC verification.
• Strong proficiency in SystemVerilog, UVM, and scripting languages such as Python, TCL, or Perl.
• Deep understanding of modern verification methodologies and flows, including constrained-random testing and coverage-

driven verification.

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