Lead Design for Test Engineer

The engineer should be well versed in Verilog RTL coding, Scan Insertion, Spyglass DRC, experienced in using Tessent DfT tools and both Synopsys and Cadence Simulation tools.

Hands on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, coverage improvement, Pattern Simulation debug with timing / SDF.

Exposure to Silicon Debug will be preferred

Location- Bangalore

EXP-8+Years