Lead Engineer-PD

Quest Global is an organization at the forefront of innovation and one of the world’s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible, possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.

As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills :

Block level implementation from netlist to GDS, Handling timing closure of high frequency blocks, Handling blocks of high instance counts – 1M instance and above, Expertise in signoff closure – Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level, Understanding constraints and fixing techniques, Understanding SI prevention , fixing methodology and implementation, Proficient in layout edit techniques, Proficient in Synopsys ICC or SoC Encounter or Mentor Olympus and Atoptech tool set., Experience in Design Automation and UNIX system. Experience in Tcl / Tk, PERL is a plus.

Desired Skills & Experience :

• Experience level 5 to 7 years.
• Must possess 5+ years of hands on experience in handling block / chip level implementation from Netlist to GDS
• Must possess hands on experience in timing closure and physical verification closure
• Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
• Understand AOCV methodology
• Experience in handling lower tech nodes that include 40nm,28nm, 22nm, 20nm, 14nm, etc
• Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC or SOC Encounter.
• Must have the ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time
• Must possess excellent scripting skills – TCL or Perl