Senior Memory Compiler Engineer

Position : Senior Memory Design Lead Engineer

Location : Bangalore

Responsibilities :

As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.

Required Skills and Experience :

• Understanding of computer architecture and concepts.
• Basic understanding of CMOS Transistors, their behaviors.
• Understanding of high speed / low power CMOS circuit design, clocking scheme, Static and complex logic circuits.
• Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.
• You have an engineering demeanor and Passion for Circuit design.
• Expected to have good interpersonal skills.
• Minimum 8+ Yrs of experience in SRAM / memory design Margin, Char and its related quality checks.

Nice To Have Skills and Experience :

Interested candidates can apply / share / refer profile at krishnaprasath.s@acldigital.com