Tenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. In this role, you’ll lead timing closure efforts across block and full-chip levels, working closely with physical design, RTL, and verification teams across multiple technology nodes, including 5nm and 3nm.
This role is onsite, based out of Bangalore.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are :
- Have 5+ yrs of hands-on experience in STA for complex SoCs, from block to full-chip level
- Comfortable using tools like PrimeTime, Tempus, or PTPX
- Strong in scripting with Tcl, Perl, or Python to automate workflows
- Confident working cross-functionally to solve timing challenges and drive closure
What We Need :
Ability to define and drive STA methodology across different corners and modesSkill in analyzing timing reports and working across teams to fix violationsExperience with timing constraints, CDC analysis, and low-power techniquesFamiliarity with MMMC flows, ECO handling, and debugging timing exceptionsWhat You Will Learn :
Navigating timing closure on advanced nodes like 5nm and 3nmCollaborating across global teams to deliver high-performance siliconImproving STA signoff processes and checklists in a fast-paced environmentSharpening debugging skills with real silicon use cases and first-silicon success targets