Senior Design Verification Engineer

Are you a hands-on verification expert looking to work on cutting-edge tech with a high-impact team? We’re expanding our engineering leadership bench across two exciting areas :

Location :

Bangalore / Hyderabad Experience :

8+ years

Position #1 : Design Verification Lead – PCIe / High-Speed Protocols We're seeking a

Design Verification Lead

to spearhead verification efforts on cutting-edge

PCIe

Ethernet PHY

designs. If you're hands-on with

SystemVerilog, UVM , and love diving deep into

high-speed protocol

logic, this is your next big opportunity. Key Responsibilities : Lead verification planning, execution, and closure for high-speed interface IPs Architect and implement UVM-based testbenches from scratch Drive test case development and protocol-level debug for PCIe (any gen) / Ethernet PHY Mentor a small team of DV engineers; own quality delivery to silicon Collaborate with design and architecture teams on spec reviews and corner cases Must-Have Skills : 8+ years in ASIC Verification, with 5+ years focused on PCIe or Ethernet Hands-on with UVM, SystemVerilog, functional coverage, assertions Experience in testbench development, regression debugging & timing-aware verification Familiarity with simulations tools (VCS / Questa / Incisive), waveform analysis, scripting Excellent communication and leadership skills Bonus Points : Experience in PHY layer debug Familiarity with VIPs and formal tools

Position #2 : Design Verification Lead – CPU Core / RISC-V We’re hiring a

Design Verification Lead

with expertise in

RISC-V, MIPS, or custom IP Processors , focused on verifying CPU internals at the

ISA level . If your comfort zone includes pipelines, branch prediction, and cache coherency, we want you on our team. Key Responsibilities : Lead verification for RISC-V / MIPS-based processor cores (not SoC-level) Interpret ISA specs to architect test plans and UVM environments Validate core features : ALUs, control logic, pipeline stages, caches, exceptions Develop assertions, coverage models, and conduct deep functional debug Interface closely with micro-architecture teams for feature bring-up and sign-off Must-Have Skills : 8+ years of experience in core verification (IP-level), especially RISC-V or MIPS Strong grasp of ISA-level testing and CPU internal features Proficient in SystemVerilog, UVM, constrained random testing Deep exposure to debug tools, waveform viewers, and code coverage Clear understanding of verification methodology, assertion-based testing Note : SoC-level DV experience alone is

not sufficient Must currently be working on

core-level verification

Interested?

Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com