VLSI Design Verification

Must Have : SV / UVM

Test Bentch Developement

Any Protocols :

PCI Express or UCIe, CXL or NVM

AXI, ACE or CHI

Ethernet, RoCE or RDMA

DDR or LPDDR or HBM)

8+ years of hands-on DV experience in System Verilog / UVM.

Must be able to own and drive the verification of a block / subsystem or a SOC.

Extensive experience in IP / sub-system and / or SoC level verification based on SV / UVM.

Must have extensive experience in verification of one or more of the following :

PCI Express or UCIe, CXL or NVM

AXI, ACE or CHI

Ethernet, RoCE or RDMA

DDR or LPDDR or HBM

ARM or RISC-V CPU based subsystem or SOC level verification using C / Assembly languages

Power Aware Simulations using UPF