ASIC Design Verification Engineer

ASIC Verification Engineer

Experience : 4+ Years

Responsibilities :

You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.

Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%)

Define, architect, code, and deliver verification suites / tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS / NC) to perform this activity. (25)

Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%)

Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)

Develop Perl, Python and / or shell scripts to improve current verification infrastructure / methodology (5%)

Required Skills :

ASIC Verification using SystemVerilog

Experience in constrained-random verification is a strong plus

Experience with verification methodology like OVM / VMM / UVM

Perl / Tcl scripting is strongly preferred

Experience verifying networking protocols such as Ethernet is desirable

Strong problem solving and ASIC debugging skills

MSEE or BSEE is required with at least 5 years of ASIC Verification Experience.